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l67132/l67142 rev. d (19 fev. 97) 1 matra mhs introduction the l67132/67142 are very low power cmos dual port static rams organized as 2048 8. they are designed to be used as a stand-alone 8 bit dual port ram or as a combination master/slave dual port for 16 bits or more width systems. the mhs master/slave dual port approach in memory system applications results in full speed, error free operation without the need for additional discrete logic. master and slave devices provide two independent ports with separate control, address and i/o pins that permit independent, asynchronous access for reads and writes to any location in the memory. an automatic power down feature controlled by cs permits the onchip circuitry of each port in order to enter a very low stand by power mode. using an array of eight transistors (8t) memory cell and fabricated with the state of the art 1.0 m m lithography named scmos, the l67132/67142 combine an extremely low standby supply current (typ = 1.0 m a) with a fast access time at 45 ns over the full temperature range. all versions offer battery backup data retention capability with a typical power consumption at less than 5 m w. for military/space applications that demand superior levels of performance and reliability the l67132/67142 is processed according to the methods of the latest revision of the mil std 883 (class b or s) and/or esa scc 9000. features single 3.3 v 0.3 volt power supply fast access time 45(*) ns to 70 ns 67132l/67142l low power 67132v/67142v very low power expandable data bus to 16 bits or more using master/slave devices when using more than one device (*) preliminary on chip arbitration logic busy output flag on master busy input flag on slave fully asynchronous operation from either port battery backup operation : 2 v data retention 2 k 8 cmos dual port ram 3.3 volt
l67132/l67142 rev. d (19 fev. 97) 2 matra mhs interface pin configuration 48 pin dil (top view), plastic, ceramic 600 mils 52 pin plcc (top view) 48 pin lcc (top view) 64 pin vqfp (top view) block diagram a 10l a 10r note : 1. l 67132 (master) : busy is open drain output and requires pullup resistor l 67142 (slave) : busy in input
l67132/l67142 rev. d (19 fev. 97) 3 matra mhs pin names left port right port names cs l cs r chip select r/w l r/w r write enable oe l oe r output enable a 0l 10l a 0r 10r address i/o 0l 7l i/o 0r 7r data input/output busy l busy r busy flag vcc power gnd ground functional description the l67132/67142 has two ports with separate control, address and i/0 pins that permit independent read/write access to any memory location. these devices have an automatic power-down feature controlled by cs . cs controls on-chip power-down circuitry which causes the port concerned to go into stand-by mode when not selected (cs high). when a port is selected access to the full memory array is permitted. each port has its own output enable control (oe ). in read mode, the port's oe turns the output drivers on when set low. non-conflicting read/write conditions are illustrated in table 1. arbitration logic the arbitration logic will resolve an address match or a chip select match down to a minimum of 5 ns and determine which port has access. in all cases, an active busy flag will be set for the inhibited port. the busy flags are required when both ports attempt to access the same location simultaneously.should this conflict arise, on-chip arbitration logic will determine which port has access and set the busy flag for the inhibited port. busy is set at speeds that allow the processor to hold the operation with its associated address and data. it should be noted that the operation is invalid for the port for which busy is set low. the inhibited port will be given access when busy goes inactive. a conflict will occur when both left and right ports are active and the two addresses coincide. the on-chip arbitration determines access in these circumstances. two modes of arbitration are provided : (1) if the addresses match and are valid before cs on-chip control logic arbitrates between cs l and cs r for access ; or (2) if the cs are low before an address match, on-chip control logic arbitrates between the left and right addresses for access (refer to table 2). the inhibited port's busy flag is set and will reset when the port granted access completes its operation in both arbitration modes. data bus width expansion master/slave description expanding the data bus width to 16 or more bits in a dual-port ram system means that several chips may be active simultaneously. if every chip has a hardware arbitrator, and the addresses for each chip arrive at the same time one chip may activate its l busy signal while another activates its r busy signal. both sides are now busy and the cpus will wait indefinitely for their port to become free. to overcome this abusy lock-outo problem, mhs has developed a master/slave system which uses a single hardware arbitrator located on the master. the slave has busy inputs which allow direct interface to the master with no external components, giving a speed advantage over other systems. when dual-port rams are expanded in width, the slave rams must be prevented from writing until the busy input has been settled. otherwise, the slave chip may begin a write cycle during a conflict situation. on the opposite, the write pulse must extend a hold time beyond busy to ensure that a write cycle occurs once the conflict is resolved. this timing is inherent in all dual-port memory systems where more than one chip is active at the same time. the write pulse to the slave must be inhibited by the master's maximum arbitration time. if a conflict then occurs, the write to the slave will be inhibited because of the master's busy signal.
l67132/l67142 rev. d (19 fev. 97) 4 matra mhs truth table table 1 : non contention read/write control (4) left or right port (1) function r/w cs oe d07 function x h x z port disabled and in power down mode. iccsb or iccsb1 l l x data in data on port written into memory (2) h l l data out data in memory output on port (3) h l h z high impedance outputs notes : 1. a ol a 10l a 0r a 10r . 2. if busy = l, data is not written. 3. if busy = l, data may not be valid, see t wdd and t ddd timing. 4. h = high, l = low, x = don't care, z = high impedance. table 2 : arbitration (5) left port right port flags function cs l a 0l a 10l cs r a 0l a 10r busy l busy r function h x h x h h no contention l any h x h h no contention h x l any h h no contention l a 0r a 10r l a 0l a 10l h h no contention address arbitration with ce low before address match l lv5r l lv5r h l lport wins l rv5l l rv5l l h rport wins l same l same h l arbitration resolved l same l same l h arbitration resolved cs arbitration with address match before cs ll5r = a 0r a 10r ll5r = a 0l a 10l h l lport wins rl5l = a 0r a 10r rl5l = a 0l a 10l l h rport wins lw5r = a 0r a 10r lw5r = a 0l a 10l h l arbitration resolved lw5r = a 0r a 10r lw5r = a 0l a 10l l h arbitration resolved notes : 5. x = don't care, l = low, h = high. lv5r = left address valid 5 ns before right address. rv5l = right address valid 5 ns before left address. same = left and right addresses match within 5 ns of each other. ll5r = left cs = low 5 ns before right cs . rl5l = right cs = low 5 ns before left cs . lw5r = left and right cs = low within 5 ns of each other.
l67132/l67142 rev. d (19 fev. 97) 5 matra mhs electrical characteristics absolute maximum ratings supply voltage (vccgnd) : 0.3 v to 7.0 v . . . . . . . . . . . . . . . . . . input or output voltage applied : (gnd 0.3 v) to (vcc + 0.3 v) . . . storage temperature : 65 c to + 150 c . . . . . . . . . . . . . . . . . . . . . . . * notice stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extented periods may affect reliability. operating range operating supply voltage operating temperature military v cc = 3.3 v 0.3 v 55 o c to + 125 o c automotive v cc = 3.3 v 0.3 v 40 o c to + 125 o c commercial v cc = 3.3 v 0.3 v 0 o c to + 70 o c industrial v cc = 3.3 v 0.3 v 40 o c to + 85 o c dc parameters ii i l67132/671424 5 l67132/671425 5 l67132/671427 0 i parameter description versio n com ind mil auto com ind mil auto com ind mil auto unit value preliminary auto auto i ccsb (6) standby supply current (both ports ttl level inputs) v l 1 5 1 10 1 5 1 10 1 5 1 10 ma ma max max i ccsb1 (7) standby supply current (both ports cmos level inputs) v l 10 100 20 200 10 100 20 200 10 100 20 200 m a m a max max i ccop (8) operating supply current (both ports active) v l 80 80 90 100 70 70 80 90 60 60 70 80 ma ma max max i ccop1 (9) operating supply current (one port active one port standby) v l 50 60 55 65 40 50 45 55 35 45 40 50 ma ma max max notes : 6. cs l = cs r 2.2 v. 7. cs l = cs r vcc 0.2 v. 8. both ports active maximum frequency outputs open oe = vih. 9. one port active (f = max) output open one port stand-by ttl or cmos level inputs cs l = cs r 2.2 v. parameter description l6713245/55/70 l6714245/55/70 unit value ii/o (10) input/output leakage current 10 m a max vil (11) input low voltage 0.7 v max vih (11) input high voltage 1.8 v min vol (12) output low voltage (i/o 0 i/o 7 ) 0.5 v max vol (13) open drain output low voltage (busy) 0.5 v max voh (12) output high voltage 1.5 v min c in (17) input capacitance 5 pf max c out (17) output capacitance 7 pf max notes : 10. v cc = 5 v, vin = gnd to v cc , cs = vih, vout = 0 to v cc . 11. vih max = v cc + 0.3 v, vil min 0.3 v or 1 v pulse width 50 ns. 12. v cc min, iol = 4 ma, ioh = 4 ma. 13. i ol = 16 ma.
l67132/l67142 rev. d (19 fev. 97) 6 matra mhs data-retention mode mhs cmos rams are designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules insure data retention : 1 chip select (cs ) must be held high during data retention ; within vcc to vcc dr . 2 cs must be kept between v cc 0.2 v and 70 % of vcc during the power up and power down transitions. 3 the ram can begin operation > trc after vcc reaches the minimum operating voltage (3 volts). timing max parameter test conditions (14) com mil ind auto unit icc dr1 @ vcc dr = 2 v 10 20 m a notes : 14. cs = vcc, vin = gnd to vcc. ac test conditions input pulse levels : gnd to 3.0 v input rise/fall times : 5 ns input timing reference levels : 1.5 v figure 1. output load. output reference levels : 1.5 v output load : see figures 1, 2 figure 2. output load. (for t hz , t lz , t wz , and t ow )
l67132/l67142 rev. d (19 fev. 97) 7 matra mhs ac parameters read cycle parameter l6713245 l6714245 l6713255 l6714255 l6713270 l6714270 unit symbol symbol parameter min. max. min. max. min. max. unit symbol (19) symbol (20) preliminary tavav r t rc read cycle time 45 55 70 ns tavqv t aa address access time 45 55 70 ns telqv t acs chip select access time (18) 45 55 70 ns tglqv t aoe output enable access time 30 35 40 ns tavqx t oh output hold from address change 0 0 0 ns telqz t lz output low z time (16, 17) 5 5 5 ns tehqz t hz output high z time (16, 17) 20 30 35 ns tpu t pu chip select to power up time (17) 0 0 0 ns tpd t pd chip disable to power down time (17) 50 50 50 ns notes : 16. transition is measured 500 mv from low or high impedance voltage with load (figures 1 and 2). 17. this parameter is guaranteed but not tested. 18. to access ram cs = vil. 19. std symbol. 20. alt symbol. timing waveform of read cycle n o 1, either side (21, 22, 24) timing waveform of read cycle n o 2, either side (21, 23, 25) notes : 21. r/w is high for read cycles. 22. device is continuously enabled, cs = vil. 23. addresses valid prior to or coincident with cs transition low. 24. oe = v il . 25. to access ram, cs = v il .
l67132/l67142 rev. d (19 fev. 97) 8 matra mhs ac parameters write cycle parameter l6713245 l6714245 l6713255 l6714255 l6713270 l6714270 unit symbol symbol parameter min. max. min. max. min. max. unit symbol (30) symbol (31) preliminary tavav w t wc write cycle time 45 55 70 ns telwh t sw chip select to end of write (28) 35 40 45 ns tavwh t aw address valid to end of write 35 40 45 ns tavwl t as address setup time 0 0 0 ns twlwh t wp write pulse width 35 40 45 ns twhax t wr write recovery time 0 0 0 ns tdvwh t dw data valid to end of write 25 25 30 ns tghqz t hz output high z time (26, 27) 20 30 40 ns twhdx t dh data hold time (29) 0 0 0 ns twlqz t wz write enable to output in high z (26, 27) 20 30 40 ns twhqx t ow output active from end of write (26, 27, 29) 0 0 0 ns notes : 26. transition is measured 500 mv from low or high impedance voltage with load (figures 1 and 2). 27. this parameter is guaranteed but not tested. 28. to access ram cs = vil. this condition must be valid for entire t sw time. 29. the specification for t dh must be met by the device supplying write data to the ram under all operating conditions. although t dh and t ow values vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 30. std symbol. 31. alt symbol.
l67132/l67142 rev. d (19 fev. 97) 9 matra mhs timing waveform of write cycle n o 1, r/w controlled timing (32, 33, 34, 38) timing waveform of write cycle n o 2, cs controlled timing (32, 33, 34, 36) notes : 32. r/w must be high during all address transitions. 33. a write occurs during the overlap (t sw or t wp ) of a low cs and a low r/w . 34. t wr is measured from the earlier of cs or r/w going high to the end of write cycle. 35. during this period, the i/o pins are in the output state, and input signals must not be applied. 36. if the cs low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high impedance state. 37. transition is measured 500 mv from steady state with a 5 pf load (including scope and jig). this parameter is sampled and not 100 % tested. 38. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 39. to access ram, cs = vil.
l67132/l67142 rev. d (19 fev. 97) 10 matra mhs ac parameters symbol parameter l6713245 l6714245 l6713255 l6714255 l6713270 l6714270 unit symbol parameter min. max. min. max. min. max. unit busy timing (for l 67132 only) t baa busy access time to address 35 45 50 ns t bda busy disable time to address 35 40 40 ns t bac busy access time to chip select 30 35 50 ns t bdc busy disable time to chip select 25 30 40 ns t wdd write pulse to data delay (40) 70 80 90 ns t ddd write data valid to read data delay (40) 45 55 70 ns t aps arbitration priority setup time (41) 5 5 5 ns t bdd busy disable to valid data note 42 note 42 note 42 ns busy timing (for l 67142 only) t wb write to busy input (43) 0 0 0 ns t wh write hold after busy (44) 20 30 30 ns t wdd write pulse to data delay (45) 70 80 90 ns t ddd write data valid to read data delay (45) 45 55 70 ns notes : 40. port-to-port delay through ram cells from writing port to reading port, refer to atiming waveform of read with busy (for l67132 only)o. 41. to ensure that the earlier of the two ports wins. 42. t bdd is a calculated parameter and is the greater of 0, t wdd t wp (actual) or t ddd t dw (actual). 43. to ensure that the write cycle is inhibited during contention. 44. to ensure that a write cycle is completed after contention. 45. port-to-port delay through ram cells from writing port to reading port, refer to atiming waveforms of read with port to port delay (for l67142 only)o.
l67132/l67142 rev. d (19 fev. 97) 11 matra mhs timing waveform of read with busy (46, 47, 48) (for l 67132) notes : 46. to ensure that the earlier of the two port wins. 47. write cycle parameters should be adhered to, to ensure proper writing. 48. device is continuously enabled for both ports. 49. oe at l for the reading port. timing waveform of write with port-to-port (50, 51, 52) (for l 67142 only) notes : 50. assume busy = h for the writing port, and oe = l for the reading port. 51. write cycle parameters should be adhered to, to ensure proper writing. 52. device is continuously enabled for both ports.
l67132/l67142 rev. d (19 fev. 97) 12 matra mhs timing waveform of write with busy (for l 67132) timing waveform of contention cycle n o 1, cs arbitration (for l 67132 only)
l67132/l67142 rev. d (19 fev. 97) 13 matra mhs timing waveform of contention cycle n o 2, address valid abritration (for l 67132 only) (53) left address valid first : right address valid first : note : 53. cs l = cs r = v il 16 bit master/slave dual-port memory systems note : 54. no arbitration in l 67142 (slave). busy -in inhibits write in l 67142 (slave).
l67132/l67142 rev. d (19 fev. 97) 14 matra mhs ordering information c = commercial 0 to +70 c i = industrial 40 to +85 c a = automotive 40 to +125 c m = military 55 to +125 c s = space 55 to +125 c 1k = 48 pin dil ceramic 600 mils ck = 48 pin dil side-brazed 600 mils 4k = 48 pin lcc s3 = 52 pin plcc 3k = 48 pin dil plastic 600 mils rd = 64 pin vqfp 67132 = 16k (2k 8) master 67142 = 16k (2k 8) slave l = low power v = very low power el = low power and rad tolerant ev = very low power and rad tolerant blank = mhs standards /883 = mil-std 883 class b or s p883 = mil-std 883 + pind test sb/sc = scc 9000 level b/c shxxx = special customer request fhxxx = flight models (space) mhxxx = mechanical parts (space) lhxxx = life test parts (space)
45 ns 55 ns 70 ns
3.3 v 0.3 volt the information contained herein is subject to change without notice. no responsibility is assumed by matra mhs sa for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.

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